FPGA with hybrid interconnect
FPGA with register-intensive architecture
Fragmentation point and simulation site adjustment for...
Framework for hierarchical VLSI design
Framework for multiple-engine based verification tools for...
Framework for rules checking utilizing resistor,...
Freeway routing system for a gate array
Frequency dependent timing margin
Frequency divider monitor of phase lock loop
Fringe RLGC model for interconnect parasitic extraction
Full flow focus exposure matrix analysis and electrical...
Full sized scattering bar alt-PSM technique for IC...
Full sized scattering bar alt-PSM technique for IC...
Full sized scattering bar alt-PSM technique for IC...
Full sized scattering bar alt-PSM technique for IC...
Full-chip extraction of interconnect parasitic data
Fullchip functional equivalency and physical verification
Function block architecture for gate array and method for...
Function symmetry-based optimization for physical synthesis...
Function synthesizing method and apparatus, and recording...