Fullchip functional equivalency and physical verification

Details Fullchip functional equivalency and physical verification Fullchip functional equivalency and physical verification

2005-06-08

2008-07-22

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07404161

ABSTRACT:
A method for maintaining equivalency between the reference Register Transfer Logic (RTL) and the physical layout design of an integrated circuit by way of maintaining a reference netlist derived from symbolic connectivity.

REFERENCES:
patent: 5623608 (1997-04-01), Ng
patent: 5958027 (1999-09-01), Gulick
patent: 6392747 (2002-05-01), Allen et al.
patent: 6550045 (2003-04-01), Lu et al.
patent: 6574788 (2003-06-01), Levine et al.
patent: 7055118 (2006-05-01), Kamepalli et al.
patent: 2002/0129325 (2002-09-01), Tanaka
patent: 2005/0198601 (2005-09-01), Kuang et al.

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