Full-chip extraction of interconnect parasitic data

Details Full-chip extraction of interconnect parasitic data Full-chip extraction of interconnect parasitic data

2001-03-14

2002-10-08

Thomas, Tom (Department: 2811)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06463571

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to design tools for integrated circuits. More specifically, but without limitation thereto, the present invention relates to characterizing parasitic effects associated with placing each instance of a circuit building block, typically called a core, hard macro, or “hardmac”, in an integrated circuit chip design.
When a hardmac is instantiated in a chip design, coupling effects between chip level interconnects routed over the hardmac or other closely adjacent metal and the hardmac may cause the chip to malfunction. Current methods for ensuring that these coupling effects, commonly called parasitics, will not cause the chip to malfunction when the hardmac is incorporated into the chip design generally either attempt to deal with the problem from the logic design perspective or from the physical design perspective.
From the logic design perspective, the hardmac designer is expected to account for best and worst case coupling effects of the design such that the circuit will function correctly across the range of possible environmental conditions. The effectiveness of this approach depends on how accurate the prediction is of the effects from the environmental conditions, and whether the effects represent too much variance to allow for effective design.
From the physical design perspective, routing blockages or metal sheets are placed over the core to create a specific environment. In some cases, this approach is preferable, for example, to shield mixed signal blocks that contain both analog and digital circuitry. Analog circuitry does not have the noise protection of logic thresholds inherent to digital circuitry and is therefore more sensitive to coupling effects. While the metal sheet affords signal integrity and predictability, it also imposes a cost on performance due to coupling between the metal plate and interconnect lines within the hardmac. In other designs, the metal sheet may not be present, so the hardmac must be designed to operate under the worst case coupling extremes of no coupling and maximum coupling.
There are trade-offs between these approaches. If the physical designer is given complete control over the physical implementation to provide the best routing solution, the design problem may be too difficult to solve. If a precise physical implementation environment is enforced, i.e., no routing over the hardmacs, it may not be possible to meet timing objectives of the design, because the routing obstructions presented by the hardmacs could force large meandering wiring routes at the chip level. On the other hand, attempting to account for the coupling effects of routing interconnects over a hardmac and other closely adjacent metal typically requires “flattening” the hierarchical level chip design, i.e., expanding the top level of the design into a single level that includes all the lower levels and performing a parasitic extraction. A parasitic extraction predicts the impedance of each interconnect due to coupling effects from adjacent interconnects and other metal.
As the size of chip designs continues to grow exponentially through hardmac reuse, the size of corresponding chip level databases increases accordingly. This explosion of data at the very least would result in longer run times to perform parasitic extraction and therefore a longer time-to-market. Even worse, the data explosion could result in failure of design tools to operate due to capacity limitations inherent in the design tools and/or the machines on which the design tools are executed.
SUMMARY OF THE INVENTION
The present invention advantageously addresses the problems above as well as other problems by providing a method for generating a hierarchical Standard Parasitic Exchange Format file for accurately performing a full-chip extraction of interconnect parasitic data for an integrated circuit.
In one embodiment, the present invention may be characterized as a method for full-chip hierarchical extraction of interconnect parasitic data for an integrated circuit that includes the steps of (a) copying a hardmac view of an instantiated hardmac into a macro level temporary view; (b) finding an instance of the hardmac in a chip level design from a chip level detailed view; (c) calculating bounding box coordinates of the instance of the hardmac from the chip level detailed view; (d) copying coupled interconnect data inside the bounding box from the chip level detailed view into the macro level temporary view; and (e) generating a macro level SPEF file from the macro level temporary view.


REFERENCES:
patent: 6363516 (2002-03-01), Cano et al.

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