Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-07-26
2004-03-23
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06711732
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a method of fabricating an integrated circuit in a microelectronic device. More particularly, the present invention relates to a method of forming smaller lithography patterns on substrates by using phase shifting masks.
BACKGROUND OF THE INVENTION
The fabrication of integrated circuits and semiconductor devices requires the application of a lithography process to define a pattern on a substrate. A photosensitive layer on a substrate is patternwise exposed with radiation that passes through a mask having opaque and transparent regions. A commonly used mask called a binary mask is comprised of an opaque material such as chrome or chromium on a transparent substrate which is typically quartz. The electric field or aerial image that exits from the mask during an exposure has a high intensity corresponding to light passing through transparent regions and a low intensity where light has been blocked by opaque regions. The aerial image is projected onto a photosensitive film called a photoresist to form exposed regions and unexposed regions. A small amount of radiation does reach “unexposed” regions, especially near borders with exposed regions because of diffracted light. This condition limits the minimum size of the features that can be formed or resolved in the photoresist pattern. Since there is a constant demand for decreasing feature size in order to build faster circuits or for a higher density of circuits per unit area, numerous resolution enhancement techniques have been developed during the past several years.
The minimum feature size that can be printed for a given process is defined as R=k&lgr;/NA where R is the minimum resolution, k is a constant for the process, &lgr; is the exposing wavelength, and NA is the numerical aperture of the projection optics in the exposure tool. A combination of lower k and lower &lgr; coupled with a higher NA has enabled a steady reduction in technology nodes in recent years from over 250 nm to 180 nm, 130 nm, and now to 100 nm. Traditionally, k is reduced by enhancements to the mask or lithographic process such as attenuated masks, off-axis illumination (OAI), optical proximity correction (OPC), scattering bars (SB) and high contrast photoresists.
The most popular exposure tools have been g-line (436 nm) and i-line (365 nm) steppers and scanners but Deep UV (248 nm) tools have been implemented to achieve resolution in the 130 nm to 250 nm range. Currently, 193 nm exposure tools are being accepted as the primary path to the 100 nm node. With each step in &lgr; reduction, the NA has been maximized to be in a range of about 0.7 to 0.85. If all the advances in k, &lgr;, and NA are combined, the minimum feature size that can be achieved is about half wavelength. In other words, for the current technology based on 193 nm exposure tools, the smallest feature that can be reliably produced in manufacturing is about 90 to 100 nm. There is a need to push the imaging capability toward quarter wavelength with new optical enhancements since the time gap between each technology node is becoming shorter and exceeds the ability of tool manufacturers to match the pace with &lgr; and NA improvements. This is especially true for gate electrodes in transistors where the feature size is already sub-100 nm and is rapidly decreasing.
Attenuated phase shift masks have been widely introduced into manufacturing processes because they can enable a smaller resolution feature to be printed with a larger process window than with binary masks. One example is found in U.S. Pat. No. 6,210,841 in which an attenuated mask is formed by adding an attenuator material such as MoSiO
x
N
y
to portions of the substrate. The thickness of the MoSiO
x
N
y
is adjusted so that the phase of the light is shifted by 180° in regions where radiation passes through the attenuator. Scattering bars are also used to improve the resolution of the process to 130 nm.
A photoresist process is also characterized by its process latitude. That is the combination of focus and exposure dose settings that will generate a photoresist feature within a given linewidth or space width tolerance which is usually within ±10% of a targeted value. A focus latitude or depth of focus (DOF) of at least 0.4 microns and preferably near 1 micron or larger is desirable for an acceptable manufacturing process. At the same time, the dose latitude or acceptable range of exposure doses should be at least 10% (±5% about a target dose) and preferably 15% or greater. As an example, a gate feature size of 180 nm that is printed at a dose of 20 mJ/cm
2
and with a process having a DOF of 1 um and a dose latitude of 20% means that a feature sizes between 162 nm and 198 nm can be printed if the exposure dose stays within a range of 18 mJ/cm
2
to 22 mJ/cm
2
and the focal plane does not shift from best focus by more than 0.5 micron (&mgr;m) in either direction (toward plane of substrate or away from substrate). A phase shifted mask can help to increase process latitude besides improving resolution. This is valuable because expensive rework involving stripping the resist layer, recoating and re-exposing when linewidth is out of specification can be reduced which leads to a lower cost device.
An alternating phase shift (alt-PSM) approach first proposed by Levenson in 1988 appears to be the best method of achieving a quarter wavelength resolution. In the case of an alt-PSM with a single trench etched into the substrate as illustrated in
FIG. 1
a
, exposing radiation
2
passes through two transparent regions with thicknesses t
1
and t
1
+t
2
on opposite sides of an opaque region
4
. The amount of quartz
6
that has been removed in the second transparent region to form trench
7
is thickness t
2
that has been determined according to an equation (n−1)×(t
2
)=½&lgr; where n is the refractive index of the quartz
6
and &lgr; is the exposing wavelength. The result is that the phase of light exiting region with thickness t
1
(through aperture B) is 180° out of phase with the light exiting the adjacent region with thickness t
1
+t
2
(through aperture A). The phase width is shown as the distance PW. This relationship forms a higher contrast aerial image that exposes the photosensitive film on the substrate and allows smaller feature sizes to be printed with an alternating mask
3
than with a binary mask which has a uniform thickness of quartz and light of only one phase exiting apertures of the mask.
An alt-PSM
3
with a dual trench is shown in
FIG. 1
b
. Trench
8
with a depth t
3
and trench
9
with a depth t
4
are etched into quartz
6
. Distances t
3
and t
4
are adjusted so that radiation
2
that passes through alt-PSM
3
exits aperture C with a phase &thgr;° and exits aperture D with a phase (180+&thgr;)°. The distance (t
2
, t
3
, or t
4
) that a trench is etched into a mask substrate will hereafter be referred to as a phase depth.
However, fabrication of alt-PSMs has been difficult in terms of automatic phase assignment, phase inspection and repair, and cycle time which increases cost beyond what many IC manufacturers can afford. Alt-PSM has a phase conflict problem because it creates dark resist (unexposed positive tone photoresist) at all areas corresponding to a 0° to 180° transition in the mask. Meanwhile, automatic phase assignment and alt-PSM design rule for an IC layout are very crucial for real applications. Spence (U.S. Pat. No. 5,573,890) and Wang (U.S. Pat. Nos. 5,858,580 and 6,228,539) reveal double exposure alt-PSM to overcome these concerns. Spence uses an alt-PSM and a structure mask in order to achieve a new gate length and remove unwanted dark lines formed by the phase shift method. However, this solution does not avoid the difficulty of making the mask. It also does not address polysilicon interconnect lines that must shrink in dimension simultaneously with a smaller gate size in order to realize the full benefit of smaller gates. Wang uses a dark field phase shifting mask for shrinking
Chang Chung-Hsing
Dai Chang-Ming
Lin Burn J.
You Jan-Wen
Ackerman Stephen B.
Dinh Paul
Saile George O.
Siek Vuthe
Taiwan Semiconductor Manufacturing Company
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