Abstraction refinement using controllability and...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07469392

ABSTRACT:
One embodiment of the present invention provides a system that refines an abstract model. Note that abstraction refinement is commonly used in formal property verification. During operation, the system receives an abstract model which is a subset of a logic design which can be represented using a set of variables and a set of Boolean functions. Next, the system receives a safety property for the logic design which is desired to be proven. The system also receives a set of counter-examples. A counter-example is a sequence of states that violates the safety property. Note that a state is an assignment of values to the variables, which are determined using the set of Boolean functions and the variable values in the previous state. The system then determines a set of cooperative variables using the set of counter-examples. A cooperative variable is a variable that can help invalidate all counter-examples. The system then refines the abstract model using the set of cooperative variables.

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patent: 7159198 (2007-01-01), Ip et al.
patent: 2003/0225552 (2003-12-01), Ganai et al.
patent: 2004/0123254 (2004-06-01), Geist et al.
patent: 2004/0153983 (2004-08-01), McMillan
patent: 2004/0230407 (2004-11-01), Gupta et al.

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