Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-11-01
2004-11-23
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06823500
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to computer-aided design, and more particularly to a computer-aided design placement tool for performing 2-dimensional transistor placement with emphasis on reliability verification constraints in integrated circuit layout.
BACKGROUND INFORMATION
Integrated circuits comprise a collection of components, including but not limited to transistors, resistors, and capacitors, fabricated on a semiconductor substrate. The components are connected with metal interconnections, called wires, to form a system such as a microprocessor. Integrated circuit performance has been improving because the components and the wires are being fabricated in smaller sizes to increase the density of the integrated circuits. However, keeping the correct functionality of an integrated circuit intact over extended periods of usage and preventing breakdowns are new concerns that designers and computer-aided design tools need to address for circuit designs.
Circuits that function properly when fabricated often fail to work after a certain period of use. Such failures are caused by various reliability phenomena. Electromigration is a common reliability phenomenon that affects high-frequency circuits today. Electromigration refers to the migration of metal ions due to prolonged electron flow in the same direction. Electromigration causes progressive damage to metal conductors in an integrated circuit. Electromigration results in the creation of voids and hillocks in the metal interconnections, as a result of which the effective cross-section of the conductor comes down. Over time, the metal width of the interconnection is no longer sufficient to carry the current and this causes electrical opens or increased resistance which lead to circuit failure.
FIGS. 1A and 1B
are diagrams of a top view of a wire illustrating the effects of electromigration. As shown in
FIG. 1A
, a wire unaffected by electromigration has a uniform width. However, a wire having a high unidirectional current density experiences electromigration over a period of use. As shown in
FIG. 1B
, the width of the wire is no longer uniform due to electromigration.
Another reliability phenomenon is the self-heat of metal wires. Self-heat refers to the thermal breakdown of a conductor, very similar to how a filament in a bulb burns out.
FIGS. 2A and 2B
are diagrams of a top view of a wire illustrating the effects of self-heat. As shown in
FIG. 2A
, a wire unaffected by self-heat has a uniform width. However, a wire having a high density current experiences self-heat over a period of use. As shown in
FIG. 2B
, a wire affected by self-heat breaks down and is no longer uniform.
Both of these problems are caused by large currents in interconnections that are not wide enough to handle them. In any modem high-frequency integrated circuit, interconnections have to be sized based on these reliability concerns. With microprocessor designs now entering the GHz frequency ranges, it is extremely critical to optimize their design layouts for reliability verification (RV) constraints. But optimizing layouts by hand for reliability verification constraints affects a mask-designer's productivity because the amount of layout rework involved can be quite significant. However, currently available automated placement algorithms do not consider reliability verification issues.
Accordingly, there is a need for an automated design tool that minimizes reliability concerns arising from electromigration and self heat, while at the same time achieves a high layout density.
SUMMARY OF THE INVENTION
According to one embodiment of the present invention, a computerized method of creating a layout for a circuit design includes receiving a circuit design and receiving at least one layout rule based on a reliability verification constraint for the circuit design. The computerized method further includes generating a layout for the circuit design through computer automated operations wherein the layout generated satisfies the at least one layout rule based on the reliability verification constraint received for the circuit design.
Other embodiments are described and claimed.
REFERENCES:
patent: 5581475 (1996-12-01), Majors
patent: 5648910 (1997-07-01), Ito
patent: 5675501 (1997-10-01), Aoki
patent: 5737236 (1998-04-01), Maziasz et al.
patent: 5737580 (1998-04-01), Hathaway et al.
patent: 5801960 (1998-09-01), Takano et al.
patent: 5817574 (1998-10-01), Gardner
patent: 5995734 (1999-11-01), Saika
patent: 6038383 (2000-03-01), Young et al.
patent: 6077308 (2000-06-01), Carter et al.
patent: 6163877 (2000-12-01), Gupta
patent: 6189131 (2001-02-01), Graef et al.
patent: 6242807 (2001-06-01), Kazami
patent: 6253361 (2001-06-01), Buch
patent: 6286128 (2001-09-01), Pileggi et al.
patent: 6308302 (2001-10-01), Hathaway et al.
patent: 6308303 (2001-10-01), Mysore et al.
patent: 6543041 (2003-04-01), Scheffer et al.
Aipperspach et al. “A 0.2-/spl mu/m, 1.8V, SOI, 550-MHZ, 64-b PowerPC Micropocessor with Copper Interconnects”, IEEE Journal of Solid-State Circuits, vol. 34, No. 11, Feb. 15, 1999, pp. 1430-1435.*
Malinoski et al., “A test site thermal control system for at-speed manufacturing testing”, Proceedings of the 1998 International Test Conference, Oct. 18, 1998, pp. 119-128.*
Gupta et al. (“Optimal 2-D cell layout with integrated transistor folding”, 1998 IEEE/ACM International Conference on Computer-Aided Design, Nov. 8, 1998, pp. 128-135.*
Frost et al. (“RELIANT: a reliability analysis tool for VLSI interconnects”, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, May 16, 1988, pp. 27.8/1-27.8/4).*
Liew et al. (“Circuit reliability simulator for interconnect, via, and contact electromigration”, IEEE Transactions on Electron Devices, vol. 39, No. 11, Nov. 1992, pp. 2472-2479).*
Teng et al. (“iTEM: a temperature-dependent electromigration reliability diagnosis tool”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, No. 8, Aug. 1997, pp. 882-893).*
Surkan (“Design for a Network-Based Education System that Evolves by Peer and Instructor Interaction”, 1998 Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Nov. 2, 1998, pp. 275-279).*
Chowdhury et al. (“Optimum design of IC power/ground nets subject to reliability constraints”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, No. 7, Jul. 1988, pp. 787-796).*
Dalal et al. (“Design of an efficient power distribution network for the UltraSPARC0l microprocessor”, Proceedings of 1995 IEEE International Conference on Computer Design: VLSI in Computers and Processors, Oct. 2, 1995, pp. 118-123).*
Wolf et al. (“Reliability driven module generation for analog layouts”, Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, vol. 6, May 30, 1999, pp. 412-415.*
Van Genneken et al. (“Doubly folded transistor matrix layout”, IEEE International Conference on Computer-Aided Design, Nov. 7, 1988, pp. 134-137).*
Her et al. (“Cell area minimization by transistor folding”, Proceedings of European Design Automation Conference, Sep. 20, 1993, pp. 172-177).*
Gupta et al. (“XPRESS: a cell layout generator with integrated transistor folding”, Proceedings of European Design and Test Conference, Mar. 11, 1996, pp. 393-400.*
Kim et al. (“An Efficient Transistor Folding Algorithm For Row-based CMOS Layout Design”, Proceedings of the 34th Design Automation Conference, Jun. 9, 1997, pp. 456-459).*
Basaran, B., et al., “GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs”,Proceedings of the 12th International Conference on VLSI Design, 448-452, (Jan. 1999).
Gupta, A., et al., “CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells”,Proceedings fo the 34th Design Automation Conference, 452-455, (Jun. 1997).
Gupta, A., et al., “Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells”,Proceedings of the 12th International Conference on VLSI Design, 453-459, (Jan. 1999).
Gupta, A., et al., “Width Minimization o
Ganesh Kiran
Levin Artour
McCoo Miles F.
Sehgal Naresh K.
Intel Corporation
Kik Phallaka
Schwegman Lundberg Woessner & Kluth P.A.
LandOfFree
2-dimensional placement with reliability constraints for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with 2-dimensional placement with reliability constraints for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and 2-dimensional placement with reliability constraints for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3347555