Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-12
2002-10-15
Phan, Trong (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06467067
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to circuit testing techniques, and particularly to using test vectors generated as epsilon-discrepant sets for test point insertion into integrated circuits (ICs).
BACKGROUND OF THE INVENTION
Conventional logic built-in self test techniques employ linear feed-back shift registers to generate a pseudo-random bit sequence that is shifted into scan chains. The bits in the scan chain serve as test patterns for the circuit under test. However, pseudo-random bit sequences contain random pattern resistant faults, in the form of non-random bit sequences that resist the random nature of the bit pattern. These faults limit the test patterns used in the test, and hence the extent of the test.
SUMMARY OF THE INVENTION
The present invention is directed to a technique of test point insertion using test vectors generated as an epsilon-discrepant set.
In one embodiment, test points of an electronic circuit, such as an IC, having a plurality of cells and a plurality of circuit inputs are selected. A test signal is propagated through at least a portion of the circuit from each test point. Each test signal is based on a respective row of a k-wise, epsilon-discrepant matrix. Cells are identified having outputs that have a constant response to the test signal. The test points are selected as the inputs of the identified cells and the inputs of the circuit. The process is iteratively repeated until the output of the electronic circuit is reached.
In some embodiments, the set of test signals contains respective pseudo-random bit sequences. A k-wise, epsilon-discrepant matrix is constructed containing a plurality of rows of bits arranged in columns. Separate rows of the matrix are selected as separate test signals of the set.
Preferably, the matrix is constructed by constructing a first vector, l, of dimension nk, based on binary vector x,y, where n is an integer. A second vector, U, of dimension nk, is constructed based on binary vector a. Respective elements of the first and second vectors are selected as elements of the matrix such that the elements of the matrix are arranged into 2
2z
rows and 2
n
columns, where z is derived from the relationship kn2
−z
<2
−k
.
In preferred embodiments, a computer-readable medium stores computer executable process steps to generate the matrix and test a computer simulation of the electronic circuit. Preferably, a netlist for the electronic circuit defines both the electronic circuit under test and the matrix generator for use in a Logic Built-In Self-Test (LBIST) system. The computer generates the matrix, and selects rows of the matrix to serve as members of the set of test signals for the LBIST system.
REFERENCES:
patent: 5475624 (1995-12-01), West
patent: 5506852 (1996-04-01), Chakradhar et al.
patent: 5513123 (1996-04-01), Dey et al.
patent: 6345379 (2002-02-01), Khouja et al.
Andreev Alexander E.
Ivanovic Lav
Scepanovic Ranko
LSI Logic Corporation
Phan Trong
LandOfFree
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