Accelerating high-level bounded model checking

Details Accelerating high-level bounded model checking Accelerating high-level bounded model checking

2007-03-22

2010-12-14

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C714S038110, C717S104000, C717S124000, C717S141000, C703S002000, C703S015000, C703S022000

Reexamination Certificate

active

07853906

ABSTRACT:
An accelerated High-Level Bounded Model Checking method that efficiently extracts high-level information from the model, uses that extracted information to obtain an improved verification model, and applies relevant information on-the-fly to simplify the BMC-problem instances.

REFERENCES:
patent: 7318205 (2008-01-01), Levitt et al.
patent: 2004/0019468 (2004-01-01), De Moura et al.
patent: 2007/0118340 (2007-05-01), Geist et al.
patent: 2008/0072190 (2008-03-01), Jain et al.
“Iterative Abstraction using SAT-based BMC with proof Analysis”, by Aarti Gupta, Malay Ganai, Zijiang Yang, Pranav Ashar, ICCAD, Nov. 11-13, 2003, pp. 416-423, @2003 ACM.
“Bounded Model Checking for Timed Systems”, by G. Audemard, A. Cimatti, A. Kornilowicz, and R. Sebastiani, @ Springer-Verlag Berlin Heidelberg 2002.

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