Accuracy of timing analysis using region-based voltage drop...

Details Accuracy of timing analysis using region-based voltage drop... Accuracy of timing analysis using region-based voltage drop...

2005-11-29

2005-11-29

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06971079

ABSTRACT:
A method and apparatus for improving the timing accuracy of an integrated circuit through region-based voltage drop budgets is provided. Further, a method for performing timing analysis on an integrated circuit partitioned into voltage drop regions is provided. During the timing analysis, a set of logic paths segments in each voltage drop region is tested to ensure that the integrated circuit meets a set of predefined timing requirements. Logic path segments that reside in different voltage drop regions are tested using a supply voltage inputted by the respective voltage drop region.

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G Bai et al., “Simulation and Optimization of the Power Distribution Network in VLSI Circuits,” 2000 IEEE/ACM Int'l Conference on CAD, pp. 481-486.

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