Bus master for selectively disconnecting/connecting a first bus

Bus master having selective burst deferral

Bus master having selective burst initiation

Bus master interface circuit with transparent preemption of a da

Bus master which selectively attempts to fill complete entries i

Bus master with antilockup and no idle bus cycles

Bus monitor with dual port memory for storing selectable trigger

Bus monitor with selective capture of independently occuring eve

Bus monitor with time stamp means for independently capturing an

Bus protocol and method for controlling a data processor

Bus receiver power-up synchronization and error detection circui

Bus regulating system

Bus repeater

Bus request buffer circuit for interfacing between field mainten

Bus request error detection

Bus selection control in a data transmission apparatus for a mul

Bus snoop method and apparatus for computer system having CPU wi

Bus sourcing and shifter control of a central processing unit

Bus steering structure for low cost pipelined processor system

Bus structure for overlapped data transfer