I-phase controls for a computer
I-Q channel adaptive line enhancer
I.sup.2 L Full adder and ALU
I/O access method for using flags to selectively control data op
I/O Adapter with direct memory access to I/O control information
I/O Bus clock
I/O bus to system interface
I/O bus transceiver for a data processing system
I/O Bus transceiver for a data processing system
I/O cache with dual tag arrays
I/O Channel bus
I/O control system and method
I/O control system for a plurality of peripheral devices
I/O Control system for data transmission and reception between c
I/O control system having a plurality of access enabling bits fo
I/O Control system having a plurality of access enabling bits fo
I/O control system using buffer full/empty and zero words signal
I/O controller for controlling the sequencing of execution of I/
I/O controller for multiple disparate serial memories with a cac
I/O Controller for transferring data between a host processor an