Bus snoop method and apparatus for computer system having CPU wi

Details Bus snoop method and apparatus for computer system having CPU wi Bus snoop method and apparatus for computer system having CPU wi

1994-04-19

1996-11-05

Shah, Alpesh M.

Boots, shoes, and leggings

395287, 36424292, 3642434, 3642455, 364DIG1, G06F 1314

Patent

active

055727018

ABSTRACT:
Bus snoop method and apparatus for use in a computer system in which a CPU with cache is coupled to a main memory control unit for controlling a main memory unit through a bus snoop control unit, wherein when the CPU with cache occupies a bus at the time that an external bus master transfers data to the main memory unit, a transfer address for transfer of the data undergoes buffering in the bus snoop control unit and after the CPU with cache ends the execution of an instruction and opens a bus right, the bus snoop control unit transfers the data transfer address subject to buffering to the CPU with cache and a corresponding address recorded in the cache is canceled.

REFERENCES:
patent: 5119485 (1992-06-01), Ledbetter, Jr. et al.
patent: 5325503 (1994-06-01), Stevens et al.
patent: 5341487 (1994-08-01), Derwin et al.
patent: 5355467 (1994-10-01), MacWilliams et al.
patent: 5426765 (1995-06-01), Stevens et al.

Affiliated with

Also associated with

Rating

Bus snoop method and apparatus for computer system having CPU wi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bus snoop method and apparatus for computer system having CPU wi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bus snoop method and apparatus for computer system having CPU wi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2022820