Bus master which selectively attempts to fill complete entries i

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Details

364243, 3642434, 364240, 3642403, 3642624, G06F 934, G06F 1204, G06F 1316

Patent

active

049145738

ABSTRACT:
A data processing system has a bus meter, a memory capable of transferring operands requested by the bus master, and a cache for temporarily storing a selected number of the most recently transferred operands. If the memory provides an operand or a portion thereof which is insufficient in size or alignment to fill a complete entry in a line in the cache, the bus master automatically transfers additional operands adjacent in the memory to the requested operand sufficient to fill that entry.

REFERENCES:
patent: 4237543 (1980-12-01), Nishio et al.
patent: 4271466 (1981-06-01), Yamamoto et al.
patent: 4276596 (1981-06-01), Flynn et al.
patent: 4315312 (1982-02-01), Schmidt
patent: 4371928 (1983-02-01), Barlow et al.
patent: 4447878 (1984-05-01), Kinnie et al.
patent: 4467447 (1984-08-01), Takahashi et al.
patent: 4633437 (1986-12-01), Mothersole et al.

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