Boots – shoes – and leggings
Patent
1987-12-22
1990-09-25
Chan, Eddie P.
Boots, shoes, and leggings
3642292, G06F 1314, G06F 1336
Patent
active
049597752
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to a bus regulating system employing a so-called daisy chain. More particularly, the present invention is directed to a bus regulating system for changing bus usage priority with software.
Heretofore a daisy chain bus regulating system has been used. One example of such a bus regulating system is shown in FIG. 4 of the accompanying drawings. Designated in FIG. 4 is a bus regulating circuit 1 for determining a module that is permitted to use a bus, a bus 2, and a request signal line 3 for transferring a request signal *RQ by which each module requests use of the bus 2. A bus usage permit signal line 4 transfers a bus usage permit signal *BG issued by the bus regulating circuit 1 for permitting each module to use the bus 2. The bus 2 is shared by modules 10, 20 and 30. (In the present description, a signal which is a logic "0" when it is effective is associated with the sign "*" in front of the alphabetical letters that denote the signal.)
In FIG. 4, when one of the modules issues a bus usage request signal *RQ, the bus regulating circuit 1 sends a bus usage permit signal *BG to the line 4 if the bus is not occupied. Each module receives the bus usage permit signal *BG and exclusively uses the bus if it has issued the request signal *RQ. If a module has not issued the request signal *RQ, then it transfers the bus usage permit signal *BG to the next module.
In conventional systems, when the modules 10, 20 and 30 shown in FIG. 4 simultaneously issue request signals *RG, since the bus regulating system is in the form of a daisy chain, those modules closer to the left have higher bus usage priority and those closer to the right have lower bus usage priority. Therefore, bus usage priority is determined by the hardware arrangement, and a module which is processing a task with higher priority may not necessarily be allowed to use the bus with priority.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a bus regulating system which will solve the aforesaid problem and can allow use of a bus with priority according to the priority of tasks processed by modules.
To eliminate the above-mentioned problem, there is provided a bus regulating system having a plurality of modules, a bus shared by the modules, a bus regulating circuit, a bus usage permit signal line, and a bus usage permit signal line in the form of a daisy chain. The regulating system comprises overlapping request determining means for determining whether an overlapping request signal is to be issued or not when a request signal is being issued from another module, and continued use determining means for determining whether the obtained right to use the bus is to be abandoned or continuously kept after the bus has been used.
A module which is processing a task of lower priority inhibits the issuance of a request signal when a request signal is being issued from another module, and gives the right to use the bus to a module which is processing a task of higher priority. Conversely, when a module is processing a task of higher priority, it issues a request signal even if a request signal is being issued from another module, so that the right to use the bus is obtained.
When a module with the right to use the bus is processing a task of higher priority, the module does not immediately abandon but keeps the bus at the time the use of the bus is finished. When a module with the right to use the bus is processing a task of lower priority, the module immediately abandons the bus and gives the bus to a module that is processing a task of higher priority at the time the use of the bus is over.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a bus regulating system according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a bus control circuit shown in FIG. 1;
FIG. 3 is a timing chart of the bus control operation according to the embodiment of the invention; and
FIG. 4 is a block diagram of a conventional bus regulating system employing
REFERENCES:
patent: 4494192 (1985-01-01), Lew et al.
patent: 4583160 (1986-04-01), Iguma
patent: 4602327 (1986-07-01), LaViolette et al.
patent: 4630193 (1986-12-01), Kris
Elektronische Rechen Anlagen, vol. 21, No. 4, Aug. 1979, "Multiprocessor System For the Real-Time Digital Processing of Video-Image Series", Nicolae et al. pp. 171-183.
IBM Technical Disclosure Bulletin, vol. 28, No. 4, Sep. 1985, "Prioritized Data Communication System Using a Common Bus", pp. 1555-1556.
Wescon/79 Conference Record, San Francisco, CA, Sep. 18-20, 1979, Paper 28/1, "Multiprocessing With Single Board Computers--Hardware Considerations", by L. Soltesz, pp. 1-6.
Proceedings of the Fall Joint Computer Conference, Araheim, California, Nov. 14-16, 1967, vol. 31, "Intercommunication of Processors and Memory", pp. 621-633.
Chan Eddie P.
Fanuc Ltd.
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