Bus request error detection

Details Bus request error detection Bus request error detection

1995-08-02

1997-07-15

Beausoliel, Jr., Robert W.

Boots, shoes, and leggings

39518509, 3642405, G06F 1100

Patent

active

056490968

ABSTRACT:
A micro code operated microsequencer that includes a monitor, a timer, a function controller and an address controller controls the functioning of a number of operational stations which exchange address and data signals with the microsequencer over a bus. The stations have designated tasks to perform and are selectable by the controller. When the station selected performs a task that requires a read from a RAM memory, the microsequencer selects a time-out duration during which the selected station is expected to complete its assigned task which is long enough to take into account the added time needed to perform the read from memory. If the station selected performs a write task, the microsequencer selects a shorter time duration during which the selected station is expected to complete this task since no memory read is needed. If any assigned task exceeds its appropriate time-out duration, an error condition will be sensed and the microsequencer will not receive an active Continue signal from the selected stations as long as their assigned tasks remain uncompleted.

REFERENCES:
patent: 4117459 (1978-09-01), Douglas et al.
patent: 4220990 (1980-09-01), Alles
patent: 4486829 (1984-12-01), Mari et al.
patent: 5301329 (1994-04-01), Frame et al.
patent: 5412803 (1995-05-01), Barton

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