Bus selection control in a data transmission apparatus for a mul

Details Bus selection control in a data transmission apparatus for a mul Bus selection control in a data transmission apparatus for a mul

1982-04-08

1985-06-11

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 1516, G06F 1540

Patent

active

045232725

ABSTRACT:
In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals, and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is possible.

REFERENCES:
patent: 3810114 (1974-05-01), Yamada
patent: 3876987 (1975-04-01), Dalton et al.
patent: 4096572 (1978-06-01), Namimoto
patent: 4131941 (1978-12-01), Siegel et al.
patent: 4232366 (1980-11-01), Levy et al.
patent: 4394731 (1983-07-01), Flusche et al.

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