Bus master with antilockup and no idle bus cycles

Details Bus master with antilockup and no idle bus cycles Bus master with antilockup and no idle bus cycles

1990-10-19

1994-02-22

Fleming, Michael R.

Boots, shoes, and leggings

395725, 3642426, 364DIG1, 36493701, 3649424, 364DIG2, G06F 1314

Patent

active

052895831

ABSTRACT:
Bus master for use in computer system includes logic for determining the number of words remaining to be transferred in a DMA operation to supply signals to permit arbitration to start for the next DMA request, thereby avoiding an idle cycle. A timeout state machine is also included to prevent the bus master state machine from hanging in a state with no exit. Errors can be masked to permit analysis of system problems.

REFERENCES:
patent: 3905025 (1975-09-01), Davis et al.
patent: 4521848 (1985-06-01), Bruce et al.
patent: 4639859 (1987-01-01), Ott
patent: 4661905 (1987-04-01), Bomba et al.
patent: 4779195 (1988-10-01), James
patent: 5072365 (1991-12-01), Burgess et al.
patent: 5101479 (1992-03-01), Baker et al.
patent: 5140680 (1992-08-01), Best

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