Bus steering structure for low cost pipelined processor system

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G06F 300

Patent

active

040578461

ABSTRACT:
Logic circuitry is provided for controlling the transfer of data between 1) a low cost pipelined processor and its associated memory, 2) between the processor and input/output devices, and 3) between the input/output devices and memory. A plurality of unidirectional busses are provided to interface the processor and memory and a bidirectional buss is provided to interface with the input/output devices. The logic circuitry provides a control function to steer data over the proper buss structures interconnecting the processor, the memory and the input/output devices and provides those interconnections in a manner which allows the processor to overlap input and output functions.

REFERENCES:
patent: 3416139 (1968-12-01), Marx
patent: 4016546 (1977-04-01), Bennett et al.

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