Bus master having selective burst deferral

Details Bus master having selective burst deferral Bus master having selective burst deferral

1987-09-21

1989-03-28

Heckler, Thomas M.

Boots, shoes, and leggings

36424341, 3642461, G06F 1208

Patent

active

048169978

ABSTRACT:
A data processing system having a bus master, a cache, and a memory which is capable of transferring operands in bursts in response to a burst request signal provided by the bus master. The bus master will provide the burst request signal to the memory in order to fill a line in the cache only if there are no valid entries in that cache line. If a requested operand spans two cache lines, the bus master will defer the burst request signal until the end of the transfer of that operand, so that only the second cache line will be burst filled.

REFERENCES:
patent: 4370712 (1983-01-01), Johnson et al.
patent: 4558429 (1985-12-01), Barlow et al.
patent: 4564899 (1986-01-01), Holly et al.

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