Bus repeater

Details Bus repeater Bus repeater

1983-04-15

1986-08-05

Thomas, James D.

Boots, shoes, and leggings

G06F 1336, G06F 1340

Patent

active

046046895

ABSTRACT:
Method and apparatus for allowing multiple enclosures (10) to be connected so that their respective motherboards (15) together define a single bus. System-wide arbitration is carried out asynchronously on an enclosure basis while arbitration within each enclosure occurs synchronously. A bus repeater (20, 25, 25') is provided at each of the upstream and downstream ends of each enclosure's motherboard. The upstream bus repeater (20) in a given enclosure is coupled by a flexible connector cable (30) to the downstream bus repeater (25, 25') in the enclosure immediately upstream. One of the bus repeaters (say the upstream one) has the status as master or arbiter while the other has the status of a slave. The connector cables have two sets of lines (32, 35), thereby allowing the bus repeaters to pass two basic types of signals: (a) bused signals (address, data) which are made available to the relevant unit boards; and (b) private signals which are passed only to the bus repeaters. The set of private signals comprises two subsets (i) downstream bound, and (ii) upstream bound, each subset of which includes request, busy, grant, and arbitrate signals. Within each enclosure, the bus repeaters monitor the local bus request and bus busy lines, and logically combine them with the upstream bound and downstream bound private request and busy signals.

REFERENCES:
patent: 3886524 (1975-05-01), Appelt
patent: 4115854 (1978-09-01), Capowski et al.
patent: 4148011 (1979-04-01), McLagan
patent: 4257095 (1981-03-01), Nadir
patent: 4281381 (1981-07-01), Ahuja
patent: 4320457 (1982-03-01), Tanikawa
patent: 4356550 (1982-10-01), Katzman et al.
patent: 4365294 (1982-12-01), Stokken

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