Multi-layered metal routing technique
Multi-layered metal routing technique
Multi-level interconnections for an integrated circuit chip
Multilevel imprint lithography
Multiuse input/output connector arrangement for graphics...
NAND flash memory with unequal spacing between signal lines
Nanoscopic wire-based devices and arrays
Non-volatile memory device and method of fabricating the same
Non-volatile programmable memory device
Non-volatile semiconductor memory and fabricating method...
Non-volatile semiconductor memory device with voltage stabilizin
Nonvolatile semiconductor memory
Nonvolatile semiconductor memory
On-chip embedded thermal antenna for chip cooling
Pattern for routing power and ground for an integrated...
Per-bit set-up and hold time adjustment for double-data rate...
Peripheral circuits of electrically programmable...
Personalizable gate array devices
Polydirectional non-orthoginal three layer interconnect architec
Power and signal routing technique for gate array design