Non-volatile semiconductor memory device with voltage stabilizin

Details Non-volatile semiconductor memory device with voltage stabilizin Non-volatile semiconductor memory device with voltage stabilizin

1992-04-15

1993-01-12

James, Andrew J.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

365185, 257316, 257494, H01L 2968, H01L 2978

Patent

active

051794276

ABSTRACT:
A NAND cell type EEPROM has parallel data transmission lines formed above a substrate, and a memory cell section including a plurality of NAND type cell units containing a NAND type cell unit that is associated with a certain bit line of the bit lines. This NAND type cell unit has a series-circuit of a preselected number of data storage transistors with control gates, and a selection transistor. A substrate voltage-stabilizing layer is insulatively provided above the substrate and positioned in the field area in adjacent to the certain bit line. The conductive layer is connected to the substrate by a contact portion so that the substrate voltage can be constantly set to a preselected voltage potential of a fixed value during the NAND type cell unit is being subjected to the write and erase modes.

REFERENCES:
patent: 4878199 (1989-10-01), Mizutani
patent: 4918501 (1990-04-01), Komori et al.
patent: 4939690 (1990-07-01), Momodomi et al.
patent: 5008856 (1991-04-01), Iwahashi
"A High Density EPROM Cell and Array", Symposium on VLSI technology digest of technical papers; P89-90; May, 1986; R. Stewart et al.

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