Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
1999-03-19
2001-09-11
Crane, Sara (Department: 2835)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S693000, C361S689000
Reexamination Certificate
active
06288418
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electronic systems and, more particularly, to methods and apparatus for providing input/output connectors capable of use with a plurality of physical connector arrangements on circuit boards.
2. History of the Prior Art
A graphics accelerator may be an integrated circuit adapted to be physically connected to a particular busing arrangement. Such an integrated circuit is typically arranged to provide input/output connections which are directly joined to busing connections on a circuit board which mounts the integrated circuit. Many graphics accelerator circuits are designed to be physically mounted to a circuit board which is adapted to be removably plugged into a slot arrangement for an input/output bus (such as the PCI or AGP buses for personal computers designed by Intel Corporation of Santa Clara, Calif.).
Circuit boards adapted to be mounted in an I/O bus slot provide a particular connection pattern to which an integrated circuit chip is typically permanently mounted. An integrated circuit chip usually has its input/output connectors designed to be mounted to a particular circuit board connection pattern which is in turn adapted to be plugged into a bus slot. The configuration of the conductors on the circuit board to which the integrated circuit must connect is controlled by the connector pattern of the slot in which the circuit board is to be placed. Consequently, the configuration of the integrated circuit input/output conductors is controlled by the connector pattern of the slot in which the circuit board is to be placed.
Instead of being physically mounted to an integrated circuit adapted to fit into an I/O bus slot, a graphics accelerator integrated circuit is sometimes mounted directly to the motherboard of a computer. In such a situation, the configuration of the integrated circuit input/output conductors is controlled by the connector pattern on the motherboard. Typically, the configuration of conductors on the motherboard to which graphics accelerator integrated circuit is mounted is different than that on a circuit board adapted to be mounted in a slot of an I/O bus. Often, the connector patterns are essentially mirror images of one another.
The consequences of this are that two individual input/output connector designs are necessary for a graphics accelerator integrated circuit which is to be placed both on a motherboard and on an I/O bus card. The requirement of different designs leads to a requirement for two different integrated circuits. This significantly increases the expense of designing and manufacturing graphics accelerator integrated circuits.
One possible way in which the same integrated circuit has been connected to a plurality of circuit boards is by modifying one or the other of the circuit boards to provide a correct interface. The typical manner in which this is accomplished is by routing the conductors on the circuit board to new positions adapted to interface with the conductor arrangement on the integrated circuit. This requires that conductors be routed over and around other conductors by the use of vias and similar arrangements. This is costly and lowers the signal integrity of the conductors.
It is desirable to eliminate the need for design and manufacture of individual integrated circuits for circuitry to be mounted to different circuit board conductor patterns without requiring cross pattern routing of connecting circuitry on circuit boards to which the integrated circuit is to be mounted.
SUMMARY OF THE INVENTION
This and other desirable objects of the present invention are accomplished by an integrated circuit including a plurality of connectors for communicating with circuitry within the integrated circuit, a plurality of input/output pads for connecting to external circuitry, a plurality of multiplexors joined to the connectors and the input/output pads, means for providing an external control signal for each multiplexor for joining the plurality of connectors for communicating with circuitry within the integrated circuit to correct input/output pads for connecting to external circuitry for operating the integrated circuit.
These and other features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views.
REFERENCES:
patent: 4679194 (1987-07-01), Peters et al.
patent: 5983379 (1999-11-01), Warren
patent: 6067262 (2000-05-01), Irrinki et al.
Iwamoto Rick M.
Reed David G.
Crane Sara
Girard & Equitz LLP
Nvidia Corporation
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