Power and signal routing technique for gate array design

Details Power and signal routing technique for gate array design Power and signal routing technique for gate array design

1997-09-19

2000-07-18

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

257207, 257208, H01L 2710

Patent

active

060910909

ABSTRACT:
A layout architecture for routing local and global interconnections for a gate array integrated circuit wherein basic cells are arranged as an array with columns and rows. Local interconnection and global interconnections are routed on the first metal layer in a direction parallel to the rows (horizontal). Power supply signals and global interconnection are routed in the second metal layer in a direction parallel to the rows (horizontal). Global interconnections are routed on the third metal layer in a direction parallel to the columns (vertical).

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