Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
2001-10-15
2003-01-28
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S210000, C257S211000
Reexamination Certificate
active
06512253
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to nonvolatile semiconductor memories.
A NAND type of flash EEPROM having such a memory cell array as shown in
FIG. 1
has been hitherto known as one of nonvolatile semiconductor memories.
The memory cell array of the NAND flash EEPROM is composed of a number of NAND cell units. Each of the NAND cell units has a NAND series of memory cells (e.g., 16 memory cells), a source-side select gate transistor connected between one end of the NAND series of memory cells and a source line, and a drain-side select gate transistor connected between the other end of the NAND string and a bit line BLi.
The memory cell array is composed of a plurality of blocks BLkj. Control gate electrodes (word lines) CG
0
to CG
15
, source-side select gate electrodes SGS, and drain-side select gate electrodes SGD extend in the row direction, while bit lines BLi extend in the column direction. A plurality of memory cells M
0
to Mi connected to one word line forms a unit called PAGE.
Usually a page of data is read out in a single read operation. The read page of data is latched by a latch circuit and then output serially to the outside of the memory chip.
For such a NAND flash EEPROM it is important to obtain a large storage capacity and reduce the area of the memory cell array for small chip sizes. To this end, it is required to reduce the size of memory cells and the spacing between two adjacent select gate lines (electrodes).
Usually the select gate line is provided with contact areas, which are large in area and prevent the spacing between two adjacent select gate lines from being reduced. When, in patterning the contact areas, misalignment occurs between the select gate line and the contact area due to resist misalignment, the resistance of the select gate line increases.
To the contact areas of the select gate line is connected a select gate bypass line, which is formed on an interlayer insulator on the word line (control gate line). In this case, in a read operation, capacitive coupling between the select gate bypass line and the word line may cause the potential on the selected word line in a selected block to rise in error.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to reduce the spacing between two adjacent select gate lines (electrodes) independently of the size of contact areas and prevent the resistance of the select gate lines from increasing even if misalignment occurs between a select gate line and its associated contact areas in patterning the contact areas.
It is the other object of the present invention to prevent the potential on the selected word line in a selected block from varying in a read operation by devising a novel layout for select gate bypass lines on an interlayer insulator on word lines.
A nonvolatile semiconductor memory of the present invention has first and second select gate electrodes formed above the surface of a semiconductor substrate to be adjacent to each other in the column direction and extend in the row direction and a diffused layer formed in a region of the semiconductor substrate between regions of the semiconductor substrate that are located below the first and second select gate electrodes. Each of the first ad second select gate electrodes is composed of a first conductive layer and a second conductive layer located above the first conductive layer. The first conductive layer of the first select gate electrode has a plurality of first contact areas therefor, and the second conductive layer of the first select gate electrode has its portions removed that are located over the first contact areas. The first conductive layer of the second select gate electrode has a plurality of second contact areas therefor, and the second conductive layer of the second select gate electrode has its portions removed that are located over the second contact areas. The first contact areas and the second contact areas are located so that they are not opposed to each other. The second select gate electrode has its first and second conductive layers removed in portions that are opposed to the first contact areas, and the first select gate electrode has its first and second conductive layers removed in portions that are opposed to the second contact areas.
A nonvolatile semiconductor memory of the present invention has first and second select gate electrodes formed above the surface of a semiconductor substrate to be adjacent to each other in the column direction and extend in the row direction and a diffused layer formed in a region of the semiconductor substrate between regions of the semiconductor substrate that are located below the first and second select gate electrodes. Each of the first and second select gate electrodes is composed of a first conductive layer and a second conductive layer located above the first conductive layer. The first conductive layer of the first select gate electrode has a plurality of contact areas therefor and the second conductive layer of the first select gate electrode has its portions disconnected that are located above the contact areas so that the contact areas are exposed. The length in the column direction of each of the contact areas is larger than the gate electrode of the first select gate electrode. The length in the column direction of portions of the second conductive layer of the first select gate electrode that are in contact with the contact areas is larger than the gate length of the first select gate electrode.
The second conductive layer of the first select gate electrode has a pattern such that it bends in the column direction in its portions that are in contact with the contact areas of the first conductive layer.
A nonvolatile semiconductor memory of the present invention has first and second select gate electrodes formed above the surface of a semiconductor substrate to be adjacent to each other in the column direction and extend in the row direction and a diffused layer formed in a region of the semiconductor substrate between regions of the semiconductor substrate that are located below the first and second select gate electrodes. Each of the first ad second select gate electrodes is composed of a first conductive layer and a second conductive layer located above the first conductive layer. The first conductive layer of the first select gate electrode has a plurality of first contact areas therefor, and the second conductive layer of the first select gate electrode has its portions disconnected that are located above the first contact areas so that the first contact areas are exposed. The first conductive layer of the second select gate electrode has a plurality of contact areas therefor, and the second conductive layer of the second select gate electrode has its portions disconnected that are located above the second contact areas so that the second contact areas are exposed. The first contact areas and the second contact areas are located so that they are not opposed to each other.
A non-volatile semiconductor memory of the present invention comprises: a cell unit composed of a memory cell and a select gate transistor; and a select gate bypass line which is connected to the select gate line of the select gate transistor in the cell unit, and which is formed at an upper level of the select gate line. The select gate bypass line is located in an area other than right above the control gate line of the memory cell in the cell unit.
A non-volatile semiconductor memory of the present invention comprises: a first cell unit, which is located in a first block, and which is composed of a plurality of memory cells serially or in parallel connected therebetween and a select gate transistor which is connected to the plurality of memory cells; a second cell unit, which is located in a second block adjacent to the first block, and which is composed of a plurality of memory cells serially or in parallel connected therebetween and a select gate transistor which is connected to the plurality of memory cells; and a first select gate bypass line which
Aritome Seiichi
Imamiya Kenichi
Nakamura Hiroshi
Oodaira Hideko
Shimizu Kazuhiro
Banner & Witcoff , Ltd.
Meier Stephen D.
Rose Kiesha
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