Per-bit set-up and hold time adjustment for double-data rate...

Details Per-bit set-up and hold time adjustment for double-data rate... Per-bit set-up and hold time adjustment for double-data rate...

2005-01-04

2005-01-04

Nguyen, Van Thu (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

C257S194000, C257S203000, C257S204000, C365S194000, C365S233100

Reexamination Certificate

active

06838712

ABSTRACT:
A synchronous double-data-rate semiconductor memory device is adapted to receive write data on both the rising and falling edges of a data strobe signal derived from an externally-applied system clock. In the write path circuitry for each data pin of the device, adjustable delay elements are provided to enable the adjustment of the setup and hold times of write data applied to the data pin relative to the data strobe signal. The delays are separately adjustable for data present during the rising edge of the data strobe signal and for data present during the falling edge of the data strobe signal. The setup and hold window for write data is thus optimizable on a per-bit basis rather than a per-cycle basis. In one embodiment, a delay circuit is provided for generating delaying the rising edge data and the falling edge data by different delay intervals.

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