Multi-level interconnections for an integrated circuit chip

Details Multi-level interconnections for an integrated circuit chip Multi-level interconnections for an integrated circuit chip

2005-06-24

2008-08-19

Tran, Minh-Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

C257S203000, C257S207000, C257S208000, C257S750000, C257S752000, C257S758000, C257S767000, C257S774000, C257SE23142, C257SE23143, C257SE23144, C257SE23145, C257SE23151, C257SE23152, C257SE23153

Reexamination Certificate

active

07414275

ABSTRACT:
Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts to the first and second elements and forming a pyramid or staircase of multilevel metallization layers to smooth diagonal current flow.

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