DRAM devices having an increased density layout

DRAM having a buried region contacted through a field region

DRAM having a cup-shaped storage node electrode recessed within

DRAM having a cup-shaped storage node electrode recessed...

DRAM having a guard ring and process of fabricating the same

DRAM having a large dielectric breakdown voltage between an adja

DRAM having a stacked capacitor and a method for fabricating...

DRAM having at least three layered impurity regions between...

Dram having deeper source drain region than that of an logic...

DRAM having peripheral circuitry in which source-drain interconn

DRAM having peripheral circuitry in which source-drain interconn

DRAM having peripheral circuitry in which source-drain interconn

DRAM having trench type capacitor extending through field oxide

DRAM layout with vertical FETs and method of formation

DRAM layout with vertical FETS and method of formation

DRAM matrix of basic organizational units each with pair of capa

DRAM memory capacitor having three-layer dielectric, and...

DRAM memory cell and array having pass transistors with...

DRAM memory cell and array having pass transistors with...

DRAM memory cell and memory cell array with fast read/write...