DRAM having peripheral circuitry in which source-drain interconn

Details DRAM having peripheral circuitry in which source-drain interconn DRAM having peripheral circuitry in which source-drain interconn

1995-06-01

1997-08-19

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257337, 257368, 257903, H01L 2978

Patent

active

056591918

ABSTRACT:
A MOS transistor included in a peripheral circuit of a DRAM has conductive layers for interconnection on respective surfaces of a pair of source.multidot.drain regions. The source.multidot.drain interconnection layers are electrically connected to the source.multidot.drain regions through the conductive layers. One of the pair of conductive layers is formed in the same step as a bit line of a memory cell, by the same material as the bit line. The other one of the pair of conductive layers is formed in the same step as a storage node of a capacitor of the memory cell, by using the same material as the storage node. The pair of conductive layers prevent direct connection between the source.multidot.drain interconnection layer and the source.multidot.drain regions, so that reduction in size of the source.multidot.drain regions can be realized.

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Kaga et al., "A Crown Type Stacked Capacitor Cell for a 1.5V Operation 64 DRAM", Proceedings of 37th Applied Physics Association Conference, 2nd vol., p. 582 no date.
Wakamiya et al., "Novel Stacked Capacitor Cell for 64Mb DRAM", 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70 no month.

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