DRAM layout with vertical FETs and method of formation

Details DRAM layout with vertical FETs and method of formation DRAM layout with vertical FETs and method of formation

2011-06-28

2011-06-28

Nguyen, Cuong Q (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000

Reexamination Certificate

active

07968928

ABSTRACT:
DRAM cell arrays having a cell area of less than about 4 F2comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

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