Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2011-08-02
2011-08-02
Dang, Trung (Department: 2892)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257SE27084
Reexamination Certificate
active
07989866
ABSTRACT:
DRAM cell arrays having a cell area of about 4 F2comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.
REFERENCES:
patent: 5013680 (1991-05-01), Lowrey et al.
patent: 5122848 (1992-06-01), Lee et al.
patent: 5466961 (1995-11-01), Kikuchi et al.
patent: 5804851 (1998-09-01), Noguchi et al.
patent: 5909618 (1999-06-01), Forbes et al.
patent: 5963469 (1999-10-01), Forbes
patent: 5977579 (1999-11-01), Noble
patent: 6072209 (2000-06-01), Noble et al.
patent: 6077745 (2000-06-01), Burns et al.
patent: 6150687 (2000-11-01), Noble et al.
patent: 6191470 (2001-02-01), Fobes et al.
patent: 6245600 (2001-06-01), Geissler et al.
patent: 6304483 (2001-10-01), Noble
patent: 6337497 (2002-01-01), Hanafi et al.
patent: 6372559 (2002-04-01), Crowder et al.
patent: 6410948 (2002-06-01), Tran et al.
patent: 6476434 (2002-11-01), Noble et al.
patent: 6498062 (2002-12-01), Durcan et al.
patent: 6696746 (2004-02-01), Farrar et al.
patent: 6831310 (2004-12-01), Mathew et al.
patent: 6844591 (2005-01-01), Tran
patent: 6906953 (2005-06-01), Forbes
patent: 7071043 (2006-07-01), Tang et al.
patent: 7122425 (2006-10-01), Chance et al.
patent: 7129538 (2006-10-01), Lee et al.
patent: 7214621 (2007-05-01), Nejad et al.
patent: 7244659 (2007-07-01), Tang et al.
patent: 7262089 (2007-08-01), Abbott et al.
patent: 7282401 (2007-10-01), Juengling
patent: 7285812 (2007-10-01), Tang et al.
patent: 7349232 (2008-03-01), Wang et al.
patent: 7365385 (2008-04-01), Abbott
patent: 7384849 (2008-06-01), Parekh et al.
patent: 2002/0109173 (2002-08-01), Forbes et al.
patent: 2002/0109176 (2002-08-01), Forbes et al.
Richardson et al., “A Trench Transistor Cross-Point DRAM Cell”, 1985 IEEE, pp. 714-717.
Abbott Todd R.
Manning Homer M.
Dang Trung
Micro)n Technology, Inc.
Wells St. John P.S.
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