DRAM having at least three layered impurity regions between...

Details DRAM having at least three layered impurity regions between... DRAM having at least three layered impurity regions between...

2005-08-25

2008-05-06

Nguyen, Cuong (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S330000, C257SE27086, C257SE27096

Reexamination Certificate

active

07368778

ABSTRACT:
Disclosed is a dynamic random access memory (DRAM) comprising a transistor having channel holes formed in the channel region thereof and cell gate structures formed in the channel holes. At least three layered impurity regions are formed in a semiconductor substrate between the channel holes and the at least three layered impurity regions form a source region for the transistor.

REFERENCES:
patent: 6380045 (2002-04-01), Guo
patent: 6570233 (2003-05-01), Matsumura
patent: 6844591 (2005-01-01), Tran
patent: 11-026609 (1999-01-01), None
patent: 1997-0004070 (1997-01-01), None
patent: 1998-048381 (1998-09-01), None
patent: 1020040008725 (2004-01-01), None

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