Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-08
2002-06-18
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S302000, C257S355000
Reexamination Certificate
active
06407421
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a dynamic random access memory (DRAM) having a trench-type capacitor. More particularly, the present invention relates to a DRAM having a guard ring and processes of fabricating the same.
2. Description of the Related Art
A memory device stores data at specified voltage levels in an array of the cells. Conventionally, the voltage levels represent that the data is either a logical “1” or a logical “0”. In dynamic random access memory devices, for example, the cells store the data as a charge on capacitor. When the data is read from the memory device, sense amplifiers detect the level of charge stored on a particular capacitor so as to produce a logical “1” or logical “0” output based on the stored charge.
Typically, in a DRAM fabricating process, a guard ring is formed on the peripheral circuit area to prevent electrostatic discharge from damaging the memory device.
FIGS. 1A through 1E
and
FIG. 3
illustrate a process flow of the fabrication of a DRAM having a guard ring according to a prior art.
Referring now to FIG.
1
A and
FIG. 3
, a cross-sectional view of semiconductor substrate
10
having a memory array area I and a guard ring area II is schematically shown. The semiconductor substrate
10
is selectively etched to respectively form a first trench
12
and a second trench
14
on the memory array area I and on the guard ring area II. These trenches
12
,
14
both have length-width dimensions of about 0.45 &mgr;m×0.2 &mgr;m. Next, a first thermal oxide layer
16
having dopants and a second thermal oxide layer
18
having dopants are respectively formed on the sidewalls of the first trench
12
and the second trench
14
by in-situ doping thermal oxidation.
Next, as shown in
FIG. 1B
, an organic material
20
, for example photoresist, is coated on the semiconductor substrate
10
and filled into the first trench
12
and second trench
14
by a spin coating method.
Referring to
FIG. 1C
, the organic material
20
is partially removed by reactive ion etching (RIE) to leave an organic material
20
a
within the first trench
12
and an organic material
20
b
within the second trench
14
.
As shown in
FIGS. 1C and 1D
, a wet etching step is used to remove the exposed thermal oxide layer
16
and the exposed thermal oxide layer
18
so as to leave a thermal oxide
16
a
and a thermal oxide
18
a,
while the organic material
20
a
and the organic material
20
b
are used as etching masks.
Next, referring to
FIG. 1E
, the remaining organic material
20
a
and the remaining organic material
20
b
are removed. Then, a thermal treatment is utilized so that the dopants of the thermal oxide
16
a
and the thermal oxide
18
a
are diffused into the adjacent semiconductor substrate
10
to respectively form a first doped plate
22
and a second doped plate
24
. These plates are called “buried plates” by those skilled in the art, and serve as storage electrodes of a trench-type capacitor. Next, a first doped strap
26
is formed on the upper surface of the semiconductor substrate
10
around the first trench
12
. At the same time, a second doped strap
28
is formed on the upper surface of the semiconductor substrate
10
around the second trench
14
. These straps are called “buried straps” by those skilled in the art, and connect the drain of MOS transistor formed in the subsequent step. Then, referring to
FIG. 3
, a photoresist mask is formed on the space S as shown by FIG.
3
. Next, an implantation step is performed to form a N-well
30
so that the second doped strap
28
and the second doped plate
24
are electrically connected.
According to the method described above, formation of the N-well
30
is required so that the second doped strap
28
and the second doped plate
24
are electrically connected. As a result, space S having 0.65 &mgr;m width is needed. Therefore, wafer area is wasted. Moreover, the additional photo-mask for N-well
30
adds cost to the manufacturing process.
SUMMARY OF THE INVENTION
In view of the above disadvantages, an object of the present invention is to provide a DRAM having a guard ring so as to economize the wafer area and to reduce the manufacturing cost by alteration of the trench dimension on the guard ring area.
In order to achieve the above object, a DRAM having a guard ring is provided, the DRAM comprising: a semiconductor substrate having a memory array area and a guard ring area; a first trench disposed within said semiconductor substrate on said memory array area; a second trench disposed within said semiconductor substrate on said guard ring area; a first doped strap disposed on the upper surface of said semiconductor substrate around said first trench; a second doped strap disposed on the upper surface of said semiconductor substrate around said second trench; a first doped plate disposed on said semiconductor substrate around the bottom of said first trench, and separated from said first doped strap by a predetermined distance; and a second doped plate disposed on said semiconductor substrate around the bottom of said second trench, and connected to said second doped strap.
Furthermore, in an embodiment of the present invention, the first trench and the second trench respectively have length-width dimensions of about 0.45 &mgr;m×0.2 &mgr;m and 0.2 &mgr;m×0.2 &mgr;m.
Furthermore, in another embodiment of the present invention, the first doped strap and the second doped strap comprise n-type dopants. Moreover, the first doped plate and the second doped plate can comprise n-type dopants.
Furthermore, in order to achieve the above object, a process of fabricating a DRAM having a guard ring is provided, the process comprising the steps of: (a) providing a semiconductor substrate having a memory array area and a guard ring area; (b) selectively etching said semiconductor substrate to form a first trench on said memory array area and a second trench on said guard ring area respectively, wherein the dimension of said second trench is smaller than that of said first trench; (c) respectively forming a first thermal oxide layer containing dopants and a second thermal oxide layer containing dopants on the sidewalls of said first trench and said second trench; (d) partially removing said first and said second thermal oxide layers so that the distance between the top portion of said first trench and the remaining first thermal oxide layer is larger than that between the top portion of said second trench and the remaining second thermal oxide layer; (e) performing a thermal treatment to diffuse said dopants of said first and said second thermal oxide layers into adjacent semiconductor substrate to form a first doped strap and a second doped strap respectively; (f) respectively forming a first doped plate and a second doped plate on the upper surfaces of said semiconductor substrate around said first trench and said second trench so that said first doped strap is separated from said first doped plate by a predetermined distance, and said second doped strap is connected to said second doped plate.
REFERENCES:
patent: 5945713 (1999-08-01), Voldman
patent: 6323689 (2001-11-01), Morishita
Liu Sheng M.
Tsai Tzu-Ching
Darby & Darby
Nanya Technology Corporation
Nguyen Cuong Quang
Thomas Tom
LandOfFree
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