DRAM devices having an increased density layout

Details DRAM devices having an increased density layout DRAM devices having an increased density layout

2007-05-22

2007-05-22

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S211000, C257S306000, C257S298000, C257S300000

Reexamination Certificate

active

11015993

ABSTRACT:
DRAM devices include a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and intersecting the word lines. A plurality of active regions is provided that are electrically coupled to the word lines and the bit lines. Each of the active regions defines a single unit memory cell having an area of 6F2in terms of a minimum line width F. Each of the active regions may be overlapped by only one word line and the active regions may be defined by an isolation region.

REFERENCES:
patent: 5877522 (1999-03-01), Kasai
patent: 6097621 (2000-08-01), Mori
patent: 6809364 (2004-10-01), Matsuoka et al.
patent: 6882556 (2005-04-01), Fuhrmann et al.
patent: 2004/0195594 (2004-10-01), Tran et al.
patent: 10098168 (1999-03-01), None
patent: 10200300586601 (2003-07-01), None
patent: 1020030092861 (2003-12-01), None
patent: 10-2004-0012545 (2004-02-01), None
Notice to Submit a Response for Korean Patent Application No. 10-2004-0039977 mailed on Feb. 25, 2006.

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