Large-area nanoenabled macroelectronic substrates and uses...
Large-area nanoenabled macroelectronic substrates and uses...
Large-area nanoenabled macroelectronic substrates and uses...
Large-area nonenabled macroelectronic substrates and uses...
Laser processing method, method for forming a flash memory, insu
Latch up protection and yield improvement device for IC array
Latch-up free vertical TVS diode array structure using...
Latch-up prevention for memory cells
Latch-up protection circuit for integrated circuits biased...
Latch-up resistant CMOS structure
Latchup prevention method for integrated circuits and device...
Latchup robust array I/O using through wafer via
Latchup-free fully-protected CMOS on-chip ESD protection circuit
Latchup-proof I/O circuit implementation
Late programming mask ROM and process for producing the same
Lateral bipolar junction transistor in CMOS flow
Lateral bipolar transistor
Lateral bipolar transistor and apparatus using same
Lateral bipolar transistor with additional ESD implant
Lateral bipolar type input/output protection device