Latchup robust array I/O using through wafer via

Details Latchup robust array I/O using through wafer via Latchup robust array I/O using through wafer via

2007-12-14

2010-06-22

Landau, Matthew C (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S357000, C257SE27063, C438S237000

Reexamination Certificate

active

07741681

ABSTRACT:
A structure and a method for preventing latchup. The structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits.

REFERENCES:
patent: 7498622 (2009-03-01), Chapman et al.

Affiliated with

Also associated with

Rating

Latchup robust array I/O using through wafer via does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Latchup robust array I/O using through wafer via, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Latchup robust array I/O using through wafer via will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4225090