Latch-up free vertical TVS diode array structure using...

Details Latch-up free vertical TVS diode array structure using... Latch-up free vertical TVS diode array structure using...

2011-02-01

2011-02-01

Le, Thao X (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S355000, C257S372000, C257SE27033

Reexamination Certificate

active

07880223

ABSTRACT:
A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device. The method includes a step of opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of the isolation trenches. The method further includes a step of applying an source mask for implanting a plurality of doped regions of the first conductivity type constituting a plurality of diodes wherein the isolation trenches isolating and preventing parasitic PNP or NPN transistor due to a latch-up between the doped regions of different conductivity types.

REFERENCES:
patent: 6046470 (2000-04-01), Williams et al.
patent: 6265743 (2001-07-01), Sakai et al.
patent: 6867436 (2005-03-01), Matteson et al.
patent: 2002/0113293 (2002-08-01), Robb et al.
patent: 2003/0173636 (2003-09-01), Barkhordarian
patent: 2005/0167742 (2005-08-01), Challa et al.

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