Latchup prevention method for integrated circuits and device...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S360000

Reexamination Certificate

active

10847317

ABSTRACT:
An integrated circuit preventing latchup. In the integrated circuit, an internal circuit is disposed in a substrate and has a parasitic SCR structure. At least one ESD protection circuit and active area are disposed on the substrate and coupled to a pad. A first current shunting diode has an anode coupled to the pad and a cathode coupled to a first voltage source. A second current shunting diode has a cathode coupled to the pad and an anode coupled to a second voltage source. Minority-carriers guard rings surround the first current shunting diode and the second shunting diode. Distance between the first and second current shunting diodes and the internal circuit, the active area and the ESD protection circuit exceed 80 μm.

REFERENCES:
patent: 5237395 (1993-08-01), Lee
patent: 5287241 (1994-02-01), Puar
patent: 5942932 (1999-08-01), Shen
patent: 5959820 (1999-09-01), Ker et al.
patent: 6309940 (2001-10-01), Lee
patent: 2000-0045936 (2000-07-01), None
patent: 2002-0045016 (2002-06-01), None

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