Latchup-proof I/O circuit implementation

Details Latchup-proof I/O circuit implementation Latchup-proof I/O circuit implementation

1996-12-18

1998-10-27

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257372, 257370, 257547, H01L 29772, H01L 27105

Patent

active

058281100

ABSTRACT:
An arrangement that prevents triggering of latchup in internal circuits by input/output buffers on an integrated circuit chip provides a space surrounding each active device connected to a bond pad. A ring well surrounds the space and separates the active device from the internal circuits of the chip. The ring well serves as a collector to prevent triggering latchup by the active device of the internal circuits located outside the ring well.

REFERENCES:
patent: 3955210 (1976-05-01), Bhatia et al.
patent: 5060044 (1991-10-01), Tomassetti
patent: 5111274 (1992-05-01), Tomizuka et al.
patent: 5491358 (1996-02-01), Miyata

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