4T memory with boost of stored voltage between standby and...

5-Transistor memory cell which can be reliably read and written

5-transistor memory cell with known state on power-up

50% EXE tracking circuit

5T high density NVDRAM cell

6-bulk transistor static memory cell using split wordline archit

6F 2 3-Transistor DRAM gain cell

6F 2 DRAM cell design with 3F-pitch folded digitline sense...

6F2 3-transistor DRAM gain cell

6F2 3-transistor DRAM gain cell

6F2 architecture ROM embedded DRAM

6F2 DRAM array with apparatus for stress testing an...

6F2 DRAM array with apparatus for stress testing an...

6F2 DRAM ARRAY, A DRAM ARRAY FORMED ON A SEMICONDUCTIVE...

8-T SRAM cell circuit, system and method for low leakage...

8/9 and 8/10-bit encoding to reduce peak surge currents when...

8T SRAM cell with higher voltage on the read WL

8T SRAM cell with higher voltage on the read WL

8T SRAM cell with higher voltage on the read WL

A circuit for providing a load for the charging of an EPROM cell