8T SRAM cell with higher voltage on the read WL

Details 8T SRAM cell with higher voltage on the read WL 8T SRAM cell with higher voltage on the read WL

2008-07-15

2008-07-15

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189150, C257S327000

Reexamination Certificate

active

07400523

ABSTRACT:
The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes a write transistor gated by a write word line. The circuitry also includes a read buffer circuit coupled to the SRAM cell core to read the cell without disturbing the state of the cell. The read buffer circuit includes a read transistor gated by a read word line, the read transistor coupled between a read bit-line and a read driver transistor that is further coupled to a voltage source Vss. The read driver transistor and a first driver transistor of the cell core are both gated by one output of the cell core. The read transistor has an electrical characteristic that differs from that of the core cell first driver transistor.

REFERENCES:
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patent: 6744661 (2004-06-01), Shubat
patent: 6791864 (2004-09-01), Houston
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patent: 2006/0002223 (2006-01-01), Song et al.
patent: 2006/0227595 (2006-10-01), Chuang et al.
U.S. Appl. No. 11/202,141, filed Aug. 11, 2005, Houston.

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