8-T SRAM cell circuit, system and method for low leakage...

Details 8-T SRAM cell circuit, system and method for low leakage... 8-T SRAM cell circuit, system and method for low leakage...

2007-07-06

2009-11-17

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S154000, C365S063000, C365S072000, C365S188000

Reexamination Certificate

active

07619916

ABSTRACT:
An SRAM cell has reduced gate and sub-threshold leakage currents. The SRAM cell is designed to include eight operatively coupled transistors to reduce leakage currents irrespective of data stored in the SRAM cell. The transistors lower the effective supply voltage at different nodes, when either bit ‘0’ or ‘1’ is stored in the SRAM cell. The reduced effective supply voltage is passed to other coupled transistors for minimizing leakages. The SRAM cell operates in an active mode and dissipates no dynamic power during active mode to inactive mode transition and vice-versa operations. The SRAM cell is also capable of reducing bit line leakage currents under suitable conditions.

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