6-bulk transistor static memory cell using split wordline archit

Details 6-bulk transistor static memory cell using split wordline archit 6-bulk transistor static memory cell using split wordline archit

1996-06-14

1997-08-05

Clawson, Jr., Joseph E.

Static information storage and retrieval

Systems using particular element

Flip-flop

365 51, 365 63, 365 72, 365190, 365208, G11C 11419

Patent

active

056549156

ABSTRACT:
The present invention relates to a solid-state bi-stable circuit functioning as a six-bulk transistor static memory cell, the circuit comprising a plurality of bitlines and at least a first and second reference line, all of which are positioned in parallel with a plurality of wordlines. The circuit further comprises a plurality of transistors including a first and second load transistor, a first and a second pull-down transistor and a first and a second access transistor, in which each of the plurality of transistors includes a gate, source and drain. The gates of the plurality of transistors are positioned in parallel to minimize area usage.

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1993 Symposium on VLSI Technology, May 17-19 1993/Kyoto, pp. 65-66, M. Helm et al.
APolysilicon Transistor Technology for Large Capacity SRAMs, Shuji Ikeda, et al., 1990, pp. 18.1.1-18.1.4, 1990 IEDM Conf. Proc.
A 25 um Bulk Full CMOS SRAM Cell Technology with Fully Overlapping Contacts, R.D.J. Verhaar, et al., 1990 IEEE, pp. 18.2.1-18.2.4, 1990 IEDM Conf. Proc.
A Split Wordline for 17Mb SRAM Using Polysilicon Sidewall Contacts, Kazuo Itabashi, et al., 1991 IEEE, pp. 17.41.-17.4.4, 1991 IEDM Conf. Proc.

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