6F2 DRAM ARRAY, A DRAM ARRAY FORMED ON A SEMICONDUCTIVE...

Details 6F2 DRAM ARRAY, A DRAM ARRAY FORMED ON A SEMICONDUCTIVE... 6F2 DRAM ARRAY, A DRAM ARRAY FORMED ON A SEMICONDUCTIVE...

2001-03-16

2003-04-08

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S063000, C257S906000

Reexamination Certificate

active

06545904

ABSTRACT:

TECHNICAL FIELD
This invention relates generally to a 6F
2
DRAM array, a DRAM array formed on a semiconductive substrate, a method of forming memory cells in a 6F
2
DRAM array and a method of isolating a single row of memory cells in a 6F
2
DRAM array.
BACKGROUND OF THE INVENTION
The reduction in memory cell and other circuit size required for high density dynamic random access memories (DRAMs) and other circuitry is a continuing goal in semiconductor fabrication. Implementing electric circuits involves connecting isolated devices through specific electric paths. When fabricating silicon and other material into integrated circuits, it is necessary to isolate devices built into the substrate from one another. Electrical isolation of devices as circuit density increases is a continuing challenge.
One method of isolating devices involves the formation of a semi-recessed or fully recessed oxide in the non-active (or field) area of the substrate. These regions are typically termed as “field oxide” and are formed by LOCal Oxidation of exposed Silicon, commonly known as LOCOS. One approach in forming such oxide is to cover the active regions with a layer of silicon nitride that prevents oxidation from occurring therebeneath. A thin intervening layer of a sacrificial pad oxide is provided intermediate the silicon substrate and nitride layer to alleviate stress and protect the substrate from damage during subsequent removal of the nitride layer. The unmasked or exposed field regions of the substrate are then subjected to a wet (H
2
O) oxidation, typically at atmospheric pressure and at temperatures of around 1000° C., for two to four hours. This results in field oxide growth where there is no masking nitride.
However, LOCOS structures do not necessarily lend themselves to progressively smaller feature sizes and/or increased densities. This is discussed to some extent in U.S. Pat. No. 5,700,733, filed on Jun. 27, 1995, entitled “Semiconductor Processing Methods Of Forming Field Oxide Regions On A Semiconductor Substrate” and issued to M. Manning, the disclosure of which is incorporated herein by reference for its teachings and which is assigned to the assignee of this patent document.
The above-noted patent presents a technique for using shallow trench isolation (STI) to realize a compact and robust DRAM cell having an area of 8F
2
. However, increasing demand for yet more compact and robust memory designs has continued to drive demand for even smaller cell areas.
Another alternative isolation technique uses an isolation gate structure formed between adjacent memory cells. The gate structure is biased to greatly reduce the number of mobile charge carriers in the semiconducting material beneath the isolation gate structure. This architecture has the advantage of providing extremely compact memory cells having an effective area of about 6F
2
(compared, for example, to an area of about 8F
2
for the LOCOS structures described above), resulting in a compact memory device. However, conventional isolation gate structures provide leakage charge which flows, at least in part, into the storage nodes of the memory device. The leakage charge, in turn, is a limiting factor in storage times between refresh cycles.
Additionally, for many gate-isolated DRAM structures, it may be necessary to use double row redundancy for replacement of rows of memory cells that include defects. This arises because a row that has been replaced, and thus includes storage nodes that are not being periodically refreshed or otherwise actively biased, includes memory cells that float to various voltages. In turn, this can cause a memory cell in a row that is separated from the row that has been replaced by only one isolation gate to behave inappropriately. As a result, at least some DRAMs employing isolation gates between some rows of memory cells also use an arrangement whereby both the row of memory cells that includes one or more defects, and the neighboring row that is isolated from that row by the isolation gate, are replaced with a pair of redundant rows of memory cells. In turn, this causes the DRAM integrated circuit to be larger than might be the case if other replacement arrangements for rows of memory cells that are defective were practicable.
Needed are apparatus and methods for reducing isolation leakage and access device leakage for improved, compact memory cells and memory cell arrays.
SUMMARY
In a first aspect, the present invention includes a 6F
2
DRAM array. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors each include a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween. The isolation gate includes a gate dielectric having a second thickness that is greater than the first thickness used in at least the first and second access transistors.
In another aspect, the present invention includes a method of isolating a single row of memory cells in a 6F
2
DRAM array. The method includes providing pairs of rows of memory cells. Each row includes a plurality of access devices each having a gate dielectric with a first thickness. The method also includes providing an isolation gate separating rows comprising each pair of rows. Each isolation gate has a gate dielectric with a second thickness. The second thickness is greater than the first thickness. The isolation gates are configured to isolate one of the pair of rows from another of the pair of rows in response to application of a suitable voltage.


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