Static information storage and retrieval – Systems using particular element – Semiconductive
Reexamination Certificate
2000-02-23
2001-06-26
Nelms, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Semiconductive
C365S036000, C365S181000
Reexamination Certificate
active
06252797
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese Patent Application No. HEI 11(1999)-105492 filed on Apr. 13, 1999, whose priority is claimed under 35 USC § 119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a masked ROM and a manufacturing process therefor. More particularly, the invention relates to a masked ROM having a flat-cell structure and being programmed by implantation of impurity ions, and a process for manufacturing the same.
2. Description of Related Art
Referring to FIGS.
10
(
a
) and
10
(
b
), conventional masked ROMs having the flat-cell structure are constructed to have a plurality of bit-line diffusion layers
22
and a plurality of word lines
23
composed of first conductive layers
25
and second conductive layers
26
. The word lines
23
are orthogonal to the bit-line diffusion layers
22
.
A masked ROM having such a construction is programmed by implanting ions into channel regions
24
a
using a mask of a photoresist film with openings in desired regions in such a manner that the ions penetrate the word lines
23
.
When boron ions are used for programming, for example, boron ions are usually implanted using a photoresist film having openings formed thereon in a size slightly larger than the channel region to be programmed, at an acceleration energy of 100 keV or more in order that boron ions penetrate the word lines. As a result, some boron ions penetrate deep into a substrate and some disperse laterally (in a direction parallel to the surface of the substrate).
Since semiconductor devices have become smaller and smaller in size and the widths of bit-line diffusion layers and channels have been reduced, there has arisen a problem that boron ions penetrate into channel regions adjacent to a channel region to be programmed due to the lateral dispersion of boron ions, which changes the threshold voltage of transistors and results in operation failure.
Boron ions, laterally dispersing, also penetrate into the bit-line diffusion layers and damage crystals in the substrate. As a result, the resistance of the bit-line diffusion layers rises and leakage at junctions increases.
In order to solve these problems, a method illustrated in
FIG. 11
is proposed (Japanese Unexamined Patent Publication No. HEI 5 (1993)-291537), for example. In this method, metal interconnects
37
which are referred to as lining interconnects are added on word lines
33
with intervention of an interlayer dielectric film
35
. The word lines
33
are formed on a semiconductor substrate
31
with intervention of a gate insulator
36
. The metal interconnects
37
are for reducing the resistance of bit-line diffusion layers
32
. Also the metal interconnects
37
, which are disposed above the bit-line diffusion layers
32
and used as masks in addition to the resist mask
38
at ion implantation for programming, prevent implanted ions from penetrating into other channel regions
34
than a channel region
34
a.
Other methods are also proposed. Gate electrodes of polysilicon are formed in an increased thickness on a semiconductor substrate or formed to have a two-layered structure of polysilicon and tungsten silicide. Alternatively, as shown in
FIG. 12
, tungsten silicide, which exhibits a good barrier ability against ion implantation, is formed as word lines
43
on a semiconductor substrate
41
with intervention of a gate insulator
46
. Further ion implantation is conducted at an elevated implantation energy using a resist mask
48
formed with intervention of an interlayer dielectric film
45
. Thereby, in diffusion layers
47
near gate electrodes
43
, ions are implanted not only in a channel region
44
a
near junctions of the diffusion layers
47
but also in a deeper region, so that damage to crystals at junctions of the diffusion layers
47
is avoided and leakage at the junctions are prevented (see Japanese Unexamined Patent Publication No. HEI 6(1994)-310684).
However, the method shown in
FIG. 11
requires an additional step of forming the metal interconnects
37
and thereby raises production costs. If the metal interconnects
37
are formed of aluminum, the additional step is not needed because the metal interconnects can be formed by the same step of forming other interconnects. However, there arises another problem in that it becomes impossible to conduct a thermal treatment with a high temperature for activating impurities by ion implantation for programming and for recovery from crystal defect. Further there is another new problem with regard to the alignment of the metal interconnects
37
with the bit-line diffusion layers
32
when the metal interconnects
37
are formed.
As for the method shown in
FIG. 12
, it carries out the ion implantation for programming in a state where the gate electrodes exist only above the channel regions, it is difficult to apply this method to the flat-cell structure, in which word lines
43
are orthogonal to diffusion layers
47
and therefore the word lines
43
exist also above the diffusion layers
47
.
SUMMARY OF THE INVENTION
The present invention provides a masked ROM of a flat cell structure having a plurality of bit-line diffusion layers formed in parallel in one direction in a semiconductor substrate, a plurality of word lines formed on the bit-line diffusion layers orthogonally to the bit-line diffusion layers and channel regions between the bit-line diffusion layers beneath the word lines, wherein the word line is composed of a laminated layer of a first conductive layer and a second conductive layer on the channel regions and composed of the second conductive layer on the bit-line diffusion layers.
The present invention also provides a process for manufacturing a masked ROM comprising the steps of forming a plurality of first conductive layers in parallel to each other on a semiconductor substrate; forming a plurality of bit-line diffusion layers in parallel to each other in one direction using the first conductive layers as masks; and forming, on the first conductive layers, second conductive layers having a higher barrier ability against ion implantation than the first conductive layers so that a plurality of word lines which are composed of the first and second conductive layers and are orthogonal to the bit-lines are formed.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 5306657 (1994-04-01), Yang
patent: 5406511 (1995-04-01), Nogami
patent: 5597753 (1997-01-01), Sheu et al.
Patent Abstracts of Japan, No. 05291537, Nov. 5, 1993.
Patent Abstracts of Japan, No. 06310684, Nov. 4, 1994.
Le Thong
Nelms David
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
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