Memory array biasing circuit for high speed CMOS device

Details Memory array biasing circuit for high speed CMOS device Memory array biasing circuit for high speed CMOS device

1984-12-20

1987-01-13

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

365189, 365190, G11C 1140

Patent

active

046369830

ABSTRACT:
A current limiting, process compensating circuit for CMOS memory arrays is provided. A dual transistor bias circuit is connected to each of a pair of columns of the array with a four transistor voltage reference circuit having its output connected to the gates of the active P-channel transistor of each bias circuit. A first P-channel transistor of the voltage reference circuit is sized to be less than the P-channel transistor of the bias circuit and the other three N-channel transistors are sized to be the same as the second transistor of the bias circuit and the two transistors of each memory cell in the array. As supply voltage to the array moves up or down making more or less current available, the combined circuit maintains nearly constant current on the first transistor of each bias circuit while compensating for process variation.

REFERENCES:
patent: 4433393 (1984-02-01), Oritani
patent: 4516225 (1985-05-01), Frederick

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