Memory array with readout isolation

Details Memory array with readout isolation Memory array with readout isolation

2007-03-28

2009-06-16

Nguyen, Tuan T (Department: 2824)

Static information storage and retrieval

Systems using particular element

Semiconductive

C365S148000, C365S149000

Reexamination Certificate

active

07548453

ABSTRACT:
Methods and apparatus for providing an array of passive nonlinear elements having an interface circuit that isolates the array from loading effects from external connections to the array. In one embodiment, a capacitive switching circuit is used to electrically isolate the elements in the array from the external load.

REFERENCES:
patent: 3245051 (1966-04-01), Robb
patent: 3576549 (1971-04-01), Hess et al.
patent: 3721964 (1973-03-01), Barrett et al.
patent: 3838405 (1974-09-01), Arnett et al.
patent: 4394752 (1983-07-01), Boudon et al.
patent: 4561070 (1985-12-01), Armstrong
patent: 4757475 (1988-07-01), Awaya et al.
patent: 5441907 (1995-08-01), Sung et al.
patent: 5673218 (1997-09-01), Shepard
patent: 5840608 (1998-11-01), Chang
patent: 5889694 (1999-03-01), Shepard
patent: 6055180 (2000-04-01), Gudesen et al.
patent: 6351023 (2002-02-01), Gates et al.
patent: 6385075 (2002-05-01), Taussig et al.
patent: 6586327 (2003-07-01), Shepard
patent: 6587394 (2003-07-01), Hogan
patent: 6598164 (2003-07-01), Shepard
patent: 6956757 (2005-10-01), Shepard
patent: 7149934 (2006-12-01), Shepard
patent: 7183206 (2007-02-01), Shepard
patent: 2003/0026120 (2003-02-01), Scheuerlein
patent: 2004/0160805 (2004-08-01), Rinerson et al.
patent: 2005/0030810 (2005-02-01), Shepard
patent: 2005/0067675 (2005-03-01), Shepard
patent: 2006/0013029 (2006-01-01), Shepard
patent: 2007/0028150 (2007-02-01), Shepard
patent: 2007/0253234 (2007-11-01), Nestler
“Summary Page: National Radio Institute 832,” Old-Computers.com, <http://old-computers.com/museum/computer.asp?c=884&st=1>, (Apr. 4, 2007), 2 pages.
Hodges, et al. “Analysis and Design of Digital Integrated Circuits,” McGraw-Hill Book Company, pp. 27-32.
Crawford, et al. “An Improved Tunnel Diode Memory System,” IBM Journal, (Jul. 1963) pp. 199-206.
Near, et al. “Read-Only Memory Adds To Calculator's Repertoire,” Electronics, (Feb. 3, 1969), pp. 70-77.
De Graaf, et al. “A Novel High-Density Low-Cost Diode Programmable Read Only Memory,” IEEE IEDM, session 7.6.1, (1996), pp. 189-192.
Wang, et al, “High-Current-Density Thin-Film Silicon Diodes Grown at Low Temperature,” Applied Physics Letters, vol. 85(11), (Sep. 13, 2004), pp. 2122-2124.
Hurst, “A Survey of Published Information on Universal Logic Arrays,” Microelectronics and Reliability, vol. 16, (1977), pp. 663-674.
McConnell, et al. “Diode-Transistor Logic,” Digital Electronics, Chapter 5, West Virginia University, (2002), pp. 1-14.
Berger, “Models for Contacts to Planar Devices,” Solid-State Electronics, vol. 15, (1972), pp. 145-158.
Wang, et al, “Low Temperature Thin-Film Silicon Diodes for Consumer Electronics,” Mater. Res. Soc. Symp. Proc., vol. 862, (2005), pp. A15.5.1-A15.5.6.
International Search Report for corresponding PCT Application No. PCT/US2007/007792 mailed Oct. 30, 2007 (3 pages).
Written Opinion for corresponding PCT Application No. PCT/US2007/007792 mailed Oct. 30, 2007 (7 pages).

Affiliated with

Also associated with

Rating

Memory array with readout isolation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory array with readout isolation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory array with readout isolation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4054260