Memory arrangement with a read-out circuit for a static memory c

Details Memory arrangement with a read-out circuit for a static memory c Memory arrangement with a read-out circuit for a static memory c

1991-12-13

1993-06-01

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Semiconductive

365174, G11C 1134

Patent

active

052166325

ABSTRACT:
A memory arrangement that includes a static memory cell with two MOSFETs that are connected such that an input signal for setting the memory cell is applied to one MOSFET, and the output of the other MOSFET is connected to the input of the first MOSFET, so that one MOSFET is always conductive while the other is blocked. The two MOSFETs are connected with positive feedback. In each case, the gate electrode is connected to a voltage equal to half the battery voltage. The source electrode of the first (N channel) MOSFET forms the input of the memory cell. The drain electrode of the first MOSFET is connected to the source electrode of the second (P channel) MOSFET. The blocking resistance of the drain-substrate diode of the first MOSFET is greater than the blocking resistance of the source-substrate diode of the second MOSFET. Also, the output voltage of the first (N channel) MOSFET is greater than the sum of the gate voltage and the threshold voltage of the second (P channel) MOSFET.

REFERENCES:
patent: 3416008 (1968-12-01), Memelink et al.
patent: 3918033 (1975-11-01), Case et al.
patent: 3919569 (1975-11-01), Gaensslen et al.
patent: 3975718 (1976-08-01), Goser
patent: 4459684 (1984-07-01), Chapman

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