Memory based on a four-transistor storage cell

Details Memory based on a four-transistor storage cell Memory based on a four-transistor storage cell

2001-03-08

2002-06-04

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Semiconductive

C365S189011

Reexamination Certificate

active

06400612

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to computer memories, and more particularly, to high-speed memories for use in cache memories and the like.
BACKGROUND OF THE INVENTION
Cache memories must run at speeds that match the speed of the CPU. To meet this speed requirement, the memory cells in the cache must have active gain to provide the necessary read speed. Hence, 6 transistor SRAM memory cells are typically used for cache memories. Unfortunately, these memory cells require a large area of silicon to construct. The silicon area is determined by the need to provide two wells per memory cell to accommodate the different types of transistors in the memory cells, as well as the large number of transistors.
Memory cells that require significantly less silicon area are known to the art. For example, conventional DRAM memory cells require only one transistor and one capacitor. However, these cells lack the active gain, and hence, cannot meet the speed requirements. In addition, conventional DRAMs require that data read from a memory cell be re-written, since the read operation removes a significant fraction of the charge stored on the capacitor. Hence, a “read” is actually a “read” followed by a “write”. This increases the cycle time further.
A three-transistor memory cell having active gain during the read operation is taught in U.S. Pat. No. 6,141,261, which is hereby incorporated by reference. This patent describes a memory that stores multiple bits per memory cell; however, the same memory cell can store a single bit. While this memory cell has the necessary speed, the memory taught in this patent requires that all bits of each word be written at once. Hence, if only one byte of the word is to be re-written, the contents of the remaining bytes must first be read so that the contents of these memory cells can be re-written when the write operation is performed on the byte that is to be altered. The additional read operation increases the memory write time, and hence, renders the memory unsuitable for cache applications.
Broadly, it is the object of the present invention to provide an improved semiconductor memory.
It is a further object of the present invention to provide a memory having active gain that requires less area than prior art memories.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.
SUMMARY OF THE INVENTION
The present invention is a memory organized as a two-dimensional array of data storage cells having a plurality of rows and columns. Each data storage cell has first, second, third, and fourth terminals, each data storage cell sinking a current between the first and second terminals indicative of a charge stored therein when the third terminal is at a first potential. The memory has a plurality of bit lines, one corresponding to each column. The first terminal of each data storage cell in each column is connected to the bit line corresponding to that column when the third terminal is at the first potential and each data storage cell is disconnected from that bit line when the third terminal is at a second potential. The memory also includes a plurality of column select lines and row select lines. There is one column select line corresponding to each column and one additional column select line adjacent to either the first or last column. The fourth terminal of each data storage cell in each column is connected to the column select line corresponding to that column. Similarly, there are row select lines, one corresponding to each row, the third terminal of each data storage cell in each row being connected to the row select line corresponding to that row. The second terminal of each data storage cell in each column is connected to the column select line of an adjacent column. The charge stored by each data storage cell is determined by the potential difference between the first and second terminals of that data storage cell when the third and fourth terminals of that data storage cell are held at a first potential. The memory also includes a read circuit for measuring the charge stored in a data storage cell in one of the columns. The read circuit is connected to the bit line corresponding to that column while the column select line corresponding to that column and the adjacent column select line to which the second terminals of the data storage cells in that column are connected. The read circuit applies a potential difference between that bit line and that adjacent column select line while applying the first potential to one of the row select lines. The memory also includes a write circuit for storing charge in the data storage cells in one of the columns. The write circuit is connected to the bit line corresponding to that column, the column select line corresponding to that column and the adjacent column select line to which the second terminals of the data storage cells in that column are connected. The write circuit applies a potential difference indicative of the charge to be stored in a selected one of the data storage cells in that column between that bit line and that adjacent column select line while applying the first potential to one of the row select lines and the column select line corresponding to that column.


REFERENCES:
patent: 5764571 (1998-06-01), Banks

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