Stress test for memory arrays in integrated circuits
Stress test mode
Stress test mode entry at power up for low/zero power memories
String programmable nonvolatile memory with NOR architecture
Strobed access semiconductor memory system
Structure and method for compensating for programming threshold
Structure and method for flash eprom memory erasable by sectors
Structure and method for hiding DRAM cycle time behind a...
Structure and method for measuring the channel boosting...
Structure and method for providing additional configuration memo
Structure and method for screening SRAMS
Structure and method of a column redundancy memory
Structure and method of operating an array of non-volatile...
Structure capable of simultaneously testing redundant and non-re
Structure for deselecting broken select lines in memory arrays
Structure for deselecting broken select lines in memory arrays
Structure for deselective broken select lines in memory arrays
Structure for echo IC
Structure for using a portion of an integrated circuit die
Structure for using a portion of an integrated circuit die